enum
No. | 名称 | 属性 | 説明 |
---|---|---|---|
1 |
《no identifier》 | ||
STAT_CTRL | 0x0e80 | 32 bit Status BMU Control Reg | |
STAT_LAST_IDX | 0x0e84 | 16 bit Status BMU Last Index | |
STAT_LIST_ADDR_LO | 0x0e88 | 32 bit Status List Start Addr (low) | |
STAT_LIST_ADDR_HI | 0x0e8c | 32 bit Status List Start Addr (high) | |
STAT_TXA1_RIDX | 0x0e90 | 16 bit Status TxA1 Report Index Reg | |
STAT_TXS1_RIDX | 0x0e92 | 16 bit Status TxS1 Report Index Reg | |
STAT_TXA2_RIDX | 0x0e94 | 16 bit Status TxA2 Report Index Reg | |
STAT_TXS2_RIDX | 0x0e96 | 16 bit Status TxS2 Report Index Reg | |
STAT_TX_IDX_TH | 0x0e98 | 16 bit Status Tx Index Threshold Reg | |
STAT_PUT_IDX | 0x0e9c | 16 bit Status Put Index Reg | |
STAT_FIFO_WP | 0x0ea0 | 8 bit Status FIFO Write Pointer Reg | |
STAT_FIFO_RP | 0x0ea4 | 8 bit Status FIFO Read Pointer Reg | |
STAT_FIFO_RSP | 0x0ea6 | 8 bit Status FIFO Read Shadow Ptr | |
STAT_FIFO_LEVEL | 0x0ea8 | 8 bit Status FIFO Level Reg | |
STAT_FIFO_SHLVL | 0x0eaa | 8 bit Status FIFO Shadow Level Reg | |
STAT_FIFO_WM | 0x0eac | 8 bit Status FIFO Watermark Reg | |
STAT_FIFO_ISR_WM | 0x0ead | 8 bit Status FIFO ISR Watermark Reg | |
STAT_LEV_TIMER_INI | 0x0eb0 | 32 bit Level Timer Init. Value Reg | |
STAT_LEV_TIMER_CNT | 0x0eb4 | 32 bit Level Timer Counter Reg | |
STAT_LEV_TIMER_CTRL | 0x0eb8 | 8 bit Level Timer Control Reg | |
STAT_LEV_TIMER_TEST | 0x0eb9 | 8 bit Level Timer Test Reg | |
STAT_TX_TIMER_INI | 0x0ec0 | 32 bit Tx Timer Init. Value Reg | |
STAT_TX_TIMER_CNT | 0x0ec4 | 32 bit Tx Timer Counter Reg | |
STAT_TX_TIMER_CTRL | 0x0ec8 | 8 bit Tx Timer Control Reg | |
STAT_TX_TIMER_TEST | 0x0ec9 | 8 bit Tx Timer Test Reg | |
STAT_ISR_TIMER_INI | 0x0ed0 | 32 bit ISR Timer Init. Value Reg | |
STAT_ISR_TIMER_CNT | 0x0ed4 | 32 bit ISR Timer Counter Reg | |
STAT_ISR_TIMER_CTRL | 0x0ed8 | 8 bit ISR Timer Control Reg | |
STAT_ISR_TIMER_TEST | 0x0ed9 | 8 bit ISR Timer Test Reg |
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